Cache Configuration Study for a Memory-Bound Workload
Overview
What this challenge is about.
Profile the existing inner loop on a workstation with perf to baseline L1/L2/L3 miss rates and miss latencies. Run the same loop through gem5's classic cache model under 6 configurations varying L2 size (256KB / 1MB / 4MB) crossed with L3 size (8MB / 32MB). For each, report miss rates per level and modeled stalled cycles. Project results to the two procurement SKUs. Deliver a simulation report, a procurement memo, and a 1-page executive summary highlighting which SKU wins per percentage-point margin of confidence.
The Brief
What you'll do, and what you'll demonstrate.
Measure and model cache behavior of a memory-bound CAE solver loop and recommend between two server SKUs with different cache configurations.
Earning criteria — what you'll demonstrate
- Measure cache miss rates on real hardware with perf counters
- Run a workload through a cache simulator and interpret results
- Project simulator results to actual hardware purchases
- Communicate hardware-procurement recommendations to non-engineers
Program Fit
Where this fits in your program.
Sharpens the same skills your degree expects you to demonstrate.
Skills
Skills you'll demonstrate.
Each one shows up on your verified credential.
Careers
Roles this prepares you for.
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Career mappings coming soon.