Diagnose a Memory-Hierarchy Bottleneck in a Trading-System Hot Path
Overview
What this challenge is about.
Profile a C++17 trading hot path with perf, fix cache misses with a memory-layout change, benchmark the fix. Get a verifiable certificate.
The scenario
The trading firm (latency-sensitive but not HFT, 4-person trading-tech team) considers any micro-architectural improvement a multi-year compounding edge.
The Brief
What you'll do, and what you'll demonstrate.
Profile a 14us hot path with perf, identify the dominant memory-hierarchy bottleneck, and propose a measured layout change toward a sub-6us target.
Earning criteria — what you'll demonstrate
- Use perf and Linux perf-counters to diagnose memory-hierarchy issues
- Distinguish L1, L2, and L3 miss patterns and their typical fixes
- Apply cache-aware data-layout techniques (SoA, hot/cold splitting)
- Communicate micro-architectural findings to a non-specialist tech lead
Program Fit
Where this fits in your program.
Sharpens the same skills your degree expects you to demonstrate.
Aligned coursework coming soon.
Skills
Skills you'll demonstrate.
Each one shows up on your verified credential.
- Memory Hierarchy
Apply memory hierarchy to solve real industry problems and demonstrate production-level capability.
- Performance Profiling
Apply performance profiling to solve real industry problems and demonstrate production-level capability.
- Perf
Apply perf to solve real industry problems and demonstrate production-level capability.
- Cache Optimization
Apply cache optimization to solve real industry problems and demonstrate production-level capability.
- Cpp
Apply cpp to solve real industry problems and demonstrate production-level capability.
- Documentation
Apply documentation to solve real industry problems and demonstrate production-level capability.
Careers
Career paths this challenge builds toward
Completing this challenge demonstrates skills that transfer directly to these roles: