Diagnose a Memory-Hierarchy Bottleneck in a Trading-System Hot Path
Overview
What this challenge is about.
Receive the normalizer source (around 4,000 lines of C++17), a replay harness that feeds 30 minutes of recorded market data, and host-machine specifications (Intel Xeon Gold 6342, 64GB DDR4, L1d 48KB / L2 1.25MB / L3 36MB shared). Profile the hot path with perf record + perf stat + perf c2c. Measure L1d/L2/L3 miss rates, branch-misprediction rate, IPC (instructions per cycle), and identify the top 3 contributors to the 14us latency. Propose a memory-layout change (struct-of-arrays vs. array-of-structs, hot/cold splitting, cache-line alignment), simulate impact with a benchmark prototype, predict the post-change latency. Deliver the profiling report, the perf data files, the proposed layout (with diff), the benchmark prototype, and a 5-page write-up for the trading-tech lead.
The Brief
What you'll do, and what you'll demonstrate.
Profile a 14us hot path with perf, identify the dominant memory-hierarchy bottleneck, and propose a measured layout change toward a sub-6us target.
Earning criteria — what you'll demonstrate
- Use perf and Linux perf-counters to diagnose memory-hierarchy issues
- Distinguish L1, L2, and L3 miss patterns and their typical fixes
- Apply cache-aware data-layout techniques (SoA, hot/cold splitting)
- Communicate micro-architectural findings to a non-specialist tech lead
Program Fit
Where this fits in your program.
Sharpens the same skills your degree expects you to demonstrate.
Skills
Skills you'll demonstrate.
Each one shows up on your verified credential.
Careers
Roles this prepares you for.
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