Rescue a 3x3 Convolution Accelerator on Zynq UltraScale+
Overview
What this challenge is about.
Build a line-buffer-based 3x3 convolution accelerator for Zynq UltraScale+, verify bit-exact output against golden samples, and earn your verifiable certificate.
The scenario
The company is a 22-person Tel Aviv startup that designs industrial inspection cameras used on food-processing lines, where a single camera must classify defects in real time without dropping frames. This accelerator is the imaging front end for its next-generation camera, and the logic it consumes directly competes with the SoC resources reserved for downstream classification.
The Brief
What you'll do, and what you'll demonstrate.
Design and verify a 3x3 convolution AXI-Stream accelerator in SystemVerilog that runs bit-exactly at 60 frames per second on 1920x1080 grayscale video on Zynq UltraScale+ while fitting inside the rest-of-SoC resource budget.
Earning criteria — what you'll demonstrate
- Architect a streaming line-buffer datapath that sustains one pixel per clock for real-time 3x3 convolution
- Implement and parameterize a fixed-point multiply-accumulate tree in SystemVerilog without rounding or saturation errors
- Drive AXI-Stream video interfaces correctly, including backpressure, frame boundaries, and start/end-of-line signaling
- Verify hardware against a software golden reference and reason about bit-exactness in fixed-point arithmetic
- Trade throughput against LUT and DSP utilization to meet a fixed system-on-chip resource budget
Program Fit
Where this fits in your program.
Sharpens the same skills your degree expects you to demonstrate.
Aligned coursework coming soon.
Skills
Skills you'll demonstrate.
Each one shows up on your verified credential.
- Systemverilog
Apply systemverilog to solve real industry problems and demonstrate production-level capability.
- Fpga
Apply fpga to solve real industry problems and demonstrate production-level capability.
- Axi Stream
Apply axi stream to solve real industry problems and demonstrate production-level capability.
- Image Processing
Apply image processing to solve real industry problems and demonstrate production-level capability.
- Fixed Point Arithmetic
Apply fixed point arithmetic to solve real industry problems and demonstrate production-level capability.
- Hardware Acceleration
Apply hardware acceleration to solve real industry problems and demonstrate production-level capability.
Careers
Career paths this challenge builds toward
Completing this challenge demonstrates skills that transfer directly to these roles:
FPGA Design Engineer
This challenge mirrors the core FPGA design loop: architect a streaming datapath, implement it in register-transfer-level code, close timing, and fit a resource budget. Delivering a synthesized, timing-closed accelerator on real silicon is exactly the evidence hiring teams look for.
This challenge sharpens
- systemverilog
- fpga
- hardware-acceleration
Embedded Vision Systems Architect
Building a real-time convolution front end under throughput and budget constraints develops the system-level judgment a vision architect needs to balance imaging pipelines against downstream compute on a shared system-on-chip.
This challenge sharpens
- image-processing
- axi-stream
- hardware-acceleration
Digital Signal Processing Hardware Engineer
Implementing a bit-exact fixed-point multiply-accumulate tree and mapping it onto DSP slices is the daily work of a DSP hardware engineer, where numerical precision and resource mapping decide whether a design ships.
This challenge sharpens
- fixed-point-arithmetic
- systemverilog
- fpga