Overview
What this challenge is about.
Receive anonymized PTP grandmaster + slave logs (nanosecond resolution, 30 days, 3 cabinets) plus a synthetic order-flow generator. Identify the drift pattern (likely candidate: leap-smear handling and asymmetric network paths). Implement a Hybrid Logical Clock (HLC) prototype in C++ that wraps the existing matching-engine API and falls back when PTP confidence drops below a threshold. Benchmark ordering correctness and added latency vs the current design. Deliver a 12-page diagnosis report, the HLC prototype, and a benchmark report. No production deployment required.
The Brief
What you'll do, and what you'll demonstrate.
Diagnose nanosecond-scale clock drift causing order-sequencing bugs and prototype a Hybrid Logical Clock fallback with measured correctness and latency tradeoffs.
Earning criteria — what you'll demonstrate
- Reason about physical vs logical clocks in a low-latency system
- Diagnose nanosecond-resolution timing bugs from real telemetry
- Implement Hybrid Logical Clocks against a production-shaped API
- Benchmark correctness vs added latency under realistic order flow
Program Fit
Where this fits in your program.
Sharpens the same skills your degree expects you to demonstrate.
Skills
Skills you'll demonstrate.
Each one shows up on your verified credential.
Careers
Roles this prepares you for.
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