Overview
What this challenge is about.
Read the SPSC queue source (around 200 lines of C++). For each atomic operation, classify the required ordering and verify the chosen memory_order is sufficient under both x86-TSO and ARMv8. Identify any operations that work on x86 by accident due to TSO but would race on ARM64. Propose minimum-strength fixes (release/acquire upgrades, fences where needed). Stress-test the original and fixed versions on AWS Graviton instances under ThreadSanitizer for 30 minutes per configuration. Deliver an audit report, a PR with the fixes, and a stress-test log.
The Brief
What you'll do, and what you'll demonstrate.
Audit a 4-year-old production lock-free SPSC queue against the ARMv8 memory model, ship minimum-strength ordering fixes, and validate under TSan on real ARM64 hardware.
Earning criteria — what you'll demonstrate
- Reason about x86-TSO vs. ARMv8 memory consistency models
- Audit lock-free code for sufficient atomic ordering
- Stress-test concurrent code with ThreadSanitizer at scale
- Balance correctness fixes against the latency cost they introduce
Program Fit
Where this fits in your program.
Sharpens the same skills your degree expects you to demonstrate.
Skills
Skills you'll demonstrate.
Each one shows up on your verified credential.
Careers
Roles this prepares you for.
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Career mappings coming soon.