Overview
What this challenge is about.
Design and implement 6 microbenchmarks: ROB capacity probe (varying chain length), load-store queue probe, branch mispredict cost probe, ILP saturation probe, store-to-load forwarding probe, and L1-data-cache associativity probe. Wrap each in a runner that pins to a core, runs with perf counters, and emits a JSON record. Provide a Python plotting script that produces the canonical interpretation plots. Test on 3 hardware platforms (an Intel laptop, an AMD server, and a Mac Apple Silicon). Deliver source, runner, plots, and a 14-page interpretation guide with annotated example plots.
The Brief
What you'll do, and what you'll demonstrate.
Build a portable microbenchmark suite that surfaces out-of-order execution behavior on modern x86 and ARM hardware with intelligible plots.
Earning criteria — what you'll demonstrate
- Design microbenchmarks that surface specific OoO mechanisms
- Collect and interpret hardware performance counters
- Compare OoO behavior across vendors (Intel, AMD, Apple Silicon)
- Document microarchitectural behavior pedagogically
Program Fit
Where this fits in your program.
Sharpens the same skills your degree expects you to demonstrate.
Skills
Skills you'll demonstrate.
Each one shows up on your verified credential.
Careers
Roles this prepares you for.
Real titles. Real skill bridges. Pick the one closest to your trajectory.
Career mappings coming soon.