Overview
What this challenge is about.
Implement the 5-stage pipeline with: hazard detection unit, forwarding paths (EX/MEM to EX, MEM/WB to EX), pipeline stalls for load-use hazards, and a simple static branch-not-taken predictor with flush on misprediction. Use a register file with synchronous write and asynchronous read. Drive simulation with Verilator. Pass the RV32I compliance subset (provided). Run a 5-program benchmark (sum, sort, GCD, Fibonacci, bit-count) and report cycles-per-instruction (CPI) per program. Deliver Verilog sources, testbench, compliance report, and a 6-page teaching writeup with a hazard-and-forwarding diagram.
The Brief
What you'll do, and what you'll demonstrate.
Build a working 5-stage pipelined RV32I core in synthesizable Verilog with hazard detection, forwarding, and compliance-suite validation.
Earning criteria — what you'll demonstrate
- Implement a 5-stage pipeline with correct hazard detection and forwarding
- Reason about data hazards (RAW), control hazards, and structural hazards
- Validate processor RTL against a compliance suite
- Communicate pipeline behavior visually for an engineering audience
Program Fit
Where this fits in your program.
Sharpens the same skills your degree expects you to demonstrate.
Skills
Skills you'll demonstrate.
Each one shows up on your verified credential.
Careers
Roles this prepares you for.
Real titles. Real skill bridges. Pick the one closest to your trajectory.
Career mappings coming soon.