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Computer & Information Sciences Challenges
Real-world challenges across Computer & Information Sciences. Pick the specific field you're studying, solve an actual brief, and walk away with verified, portable proof recruiters can confirm in one click.
Recommended challenges
- CodeIntermediateNew
Build a Real-Time Streaming Pipeline for Card-Fraud Scoring
Using the provided transaction-event sample, the cardholder feature snapshot, the reference scoring service, and the risk team's experiment specification, build a stream-process…
- Stream Processing
- Kafka
- Flink
Open coursework - DesignIntermediateNew
Migrate a 200TB Data Lake from Parquet to Iceberg
Receive an inventory of the 200TB hot tier (around 1,200 tables, around 38 PB of historical data referenced), the current Spark + Trino read patterns, and 6 months of schema-cha…
- Iceberg
- Parquet
- Data Lake
Big Data and Data-Intensive Systems - DesignIntermediateNew
Cut a 42-Minute Trino Query to Under Five Minutes
Using the slow query, the EXPLAIN ANALYZE readout, the Iceberg table schemas, and the 30-day execution-metrics dataset provided, design an optimization proposal that cuts the cr…
- Trino
- SQL Optimization
- Iceberg
Open coursework - CodeIntermediateNew
Design a Change-Data-Capture Pipeline for an E-Commerce Reseller
Receive the MySQL schema (220 tables), 7 days of binlog samples, and the data team's freshness + correctness requirements. Design the CDC pipeline: Debezium for MySQL binlog cap…
- Change Data Capture
- Debezium
- Kafka
Big Data and Data-Intensive Systems Practice your coursework on real scenarios.
Every challenge is shaped from real-world context — not generic exercises. The work mirrors what your degree prepares you for.
Why Ewance
- AnalysisIntermediateNew
Halve a Daily Spark Bill Without Breaking the SLA
Work only from the materials in this file. Read the representative PySpark module (PULSE-JOB) and the cluster configuration (PULSE-CLUSTER) to understand how the nightly job is …
- Spark
- Cost Optimization
- Etl Pipelines
Open coursework - CodeIntermediateNew
Build a 5-Stage Pipelined RISC-V Core in Verilog
Implement the 5-stage pipeline with: hazard detection unit, forwarding paths (EX/MEM to EX, MEM/WB to EX), pipeline stalls for load-use hazards, and a simple static branch-not-t…
- Pipelining
- Hazard Detection
- Verilog
Computer Architecture - AnalysisBeginnerNew
Cache Configuration Study for a Memory-Bound Workload
Profile the existing inner loop on a workstation with perf to baseline L1/L2/L3 miss rates and miss latencies. Run the same loop through gem5's classic cache model under 6 confi…
- Caches
- Memory Subsystems
- Performance Modeling
Computer Architecture - AnalysisIntermediateNew
Branch Predictor Study for a Cryptocurrency Hashing Library
Profile the hot inner loop with perf record + perf annotate to identify the 5 highest-frequency branches. Measure per-branch mispredict counts using perf counters (BR_MISP_RETIR…
- Branch Prediction
- Performance Counters
- Benchmarking
Open coursework - Browse challenges
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- DesignBeginnerNew
Sketch a Custom Gaussian-Blur Accelerator for a Smart-Camera Chip
Using the provided C reference implementation of the 5x5 Gaussian blur, work out a hardware datapath that produces one finished output pixel every clock cycle by sliding a 5x5 w…
- Hardware Accelerators
- Datapath Design
- Performance Modeling
Open coursework - AnalysisBeginnerNew
Instruction Set Analysis for an Embedded Workload
Compile all 12 workload programs to both ISAs using the appropriate cross-compiler (GCC with -march=rv32e for RISC-V; provided proprietary toolchain for the in-house ISA). Repor…
- Instruction Sets
- Code Density
- Embedded Systems
Computer Architecture - AnalysisIntermediateNew
Cache Coherence Protocol Comparison on a Multicore Simulator
Stand up gem5's Ruby coherence framework with both MESI and MOESI protocols on a 16-core configuration. Run the 6-benchmark suite (provided): producer-consumer queue, false-shar…
- Cache Coherence
- Multicore Architecture
- Simulation
Advanced Computer Architecture - AnalysisSeniorNew
Memory Consistency Model Audit of a Lock-Free Queue
Read the SPSC queue source (around 200 lines of C++). For each atomic operation, classify the required ordering and verify the chosen memory_order is sufficient under both x86-T…
- Memory Consistency
- Concurrency
- Lock Free Programming
Advanced Computer Architecture Build a verifiable portfolio.
Submissions become evidence. Reviewers with shipping experience score against a rubric; the result becomes a credential anyone can verify.
Why Ewance
- AnalysisIntermediateNew
GPU Roofline Model Study for a Computer Vision Inference Workload
Construct empirical roofline plots for the current GPU (A100-class) and next-gen GPU (H100-class) using vendor-published peak FLOPs and measured peak memory bandwidth. Profile t…
- Gpu Architecture
- Roofline Model
- Performance Modeling
Open coursework - CodeIntermediateNew
Out-of-Order Execution Microbenchmark Suite
Design and implement 6 microbenchmarks: ROB capacity probe (varying chain length), load-store queue probe, branch mispredict cost probe, ILP saturation probe, store-to-load forw…
- Out Of Order Execution
- Performance Counters
- Benchmarking
Advanced Computer Architecture - CodeSeniorNew
Heterogeneous Scheduling Policy for a Big.LITTLE Mobile SoC
Read the existing scheduler's energy model (provided). Design an improved policy using one or more of: per-task IPC-aware placement, exponential moving average load smoothing to…
- Multicore Architecture
- Scheduling
- Energy Modeling
Advanced Computer Architecture - AnalysisIntermediateNew
Diagnose a Memory-Hierarchy Bottleneck in a Trading-System Hot Path
Receive the normalizer source (around 4,000 lines of C++17), a replay harness that feeds 30 minutes of recorded market data, and host-machine specifications (Intel Xeon Gold 634…
- Memory Hierarchy
- Performance Profiling
- Perf
Open coursework - CodeBeginnerNew
Reverse-Engineer a Stripped Binary to Restore Linking Symbols
Receive the stripped shared object (Linux ELF, x86-64, ~280KB), a crash dump with 12 frames of indecipherable addresses, and 4 years of partial git history with some related (bu…
- Reverse Engineering
- Linking And Loading
- Machine Code
Open coursework - CodeBeginnerNew
Implement a User-Space Shell with Process and Signal Handling
Implement a shell in C (no shell helpers, just POSIX system calls). Required features: read a line, parse it into commands + arguments, handle pipelines with arbitrary chain len…
- System Calls
- Process Management
- Signal Handling
Computer Systems and Organization - AnalysisBeginnerNew
Profile and Optimize a Virtual-Memory-Heavy Image Pipeline
Receive the Go pipeline source, a representative batch (1,200 photos averaging 12MB each, with 30 outliers over 80MB), and host specs (4-core, 16GB RAM, Linux kernel 5.15). Run …
- Virtual Memory
- Performance Profiling
- Memory Hierarchy
Open coursework - CodeBeginnerNew
Build an I/O Benchmarking Harness for an Edge Storage Appliance
Receive the appliance specs (4x 7.68TB Gen4 NVMe, ZFS, Linux kernel 5.15), the 3 target workload profiles (4KB random read at QD32, 1MB sequential write at QD8, mixed 70/30 read…
- Io Benchmarking
- Fio
- System Calls
Computer Systems and Organization - CodeSeniorNew
Vectorize a Risk-Calculation Engine for a Mid-Cap Bank
Receive the existing pricer (C++17, scalar, around 600 lines), 2 weeks of representative input data (around 50M paths), the validation harness, and access to an Intel Ice Lake-S…
- Vectorization
- Avx 512
- Simd
Performance Engineering of Software Systems - CodeSeniorNew
Cache-Optimize a Graph-Analytics Kernel for a Social Platform
Receive the existing kernel (C++ + OpenMP, around 1,200 lines), the 1.8B-edge graph (CSR format, around 14GB), and target hardware (dual-socket AMD EPYC 9354, 384GB DDR5, 256MB …
- Cache Optimization
- Graph Algorithms
- Memory Hierarchy
Performance Engineering of Software Systems - AnalysisSeniorNew
Tame the P99 Latency Tail of a Real-Time Ad-Auction Service
Working from the four provided materials only, isolate and fix the latency tail of the bidder. Start with the representative auction-handler module ('bidder-module') as the code…
- Performance Optimization
- Ebpf
- Go
Open coursework - DesignIntermediateNew
Build a Scalable-System-Design Spec for a Streaming-Ingest Pipeline
Receive the current architecture (Kafka 3.6, Flink 1.18, ClickHouse 24.x), 4 weeks of production metrics (per-topic throughput, partition skew, Flink operator backpressure, Clic…
- Scalable System Design
- Kafka
- Flink
Open coursework
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Browse challenges aligned to your studies.
Step 02
Accept the one that fits your goals.
Step 03
Work through it with AI Copilot guidance.
Step 04
Submit for structured evaluation.
Step 05
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