Overview
What this challenge is about.
Compile all 12 workload programs to both ISAs using the appropriate cross-compiler (GCC with -march=rv32e for RISC-V; provided proprietary toolchain for the in-house ISA). Report static code size (ROM footprint), dynamic instruction count from cycle-accurate simulation, and estimated cycles assuming a simple 3-stage in-order pipeline. Identify which workload classes favor each ISA (e.g. tight loops vs. control-heavy code). Deliver per-program numbers, a workload-mix-weighted summary, and a 10-page recommendation memo with risks and migration cost.
The Brief
What you'll do, and what you'll demonstrate.
Compare an in-house 16-bit ISA against RV32E on a 12-program embedded workload and recommend a next-generation MCU ISA to the CTO.
Earning criteria — what you'll demonstrate
- Cross-compile real embedded workloads to multiple ISAs
- Measure code size and dynamic instruction count rigorously
- Map ISA-feature differences to observed workload behavior
- Translate measurement to a strategic ISA recommendation
Program Fit
Where this fits in your program.
Sharpens the same skills your degree expects you to demonstrate.
Skills
Skills you'll demonstrate.
Each one shows up on your verified credential.
Careers
Roles this prepares you for.
Real titles. Real skill bridges. Pick the one closest to your trajectory.
Product Manager
Hardware-product PMs who understand ISA migration cost set realistic roadmaps and avoid the silicon-bring-up surprises that kill quarters.
This challenge sharpens
- benchmarking
- stakeholder-communication
- embedded-systems