Sketch a Custom Gaussian-Blur Accelerator for a Smart-Camera Chip
Overview
What this challenge is about.
Design a 5x5 Gaussian-blur datapath for a smart-camera chip, compare it against a CPU, and make a go/no-go call. Get a verifiable certificate.
The scenario
The company builds smart-home cameras and doorbells whose image quality and battery life both hinge on how efficiently the main chip processes each frame. On low-power camera silicon, moving a hot per-frame operation from software into a dedicated hardware block is a classic way to reclaim time budget and energy, but chip area is rationed and every block competes for it.
The Brief
What you'll do, and what you'll demonstrate.
Decide whether a dedicated hardware accelerator for the per-frame 5x5 Gaussian blur earns a scarce silicon slot, by sketching its architecture and estimating its area, power, and throughput well enough to defend the recommendation.
Earning criteria — what you'll demonstrate
- Translate a software image-processing routine into a streaming hardware datapath that sustains one output pixel per cycle
- Size on-chip line-buffer memory for a given image resolution and window
- Produce defensible area and power estimates from published process norms, with explicit sensitivity bounds
- Build a fair software-versus-hardware comparison on throughput, energy per pixel, and area
- Write a decision-grade concept document that survives scrutiny from a chip team rationing silicon
Program Fit
Where this fits in your program.
Sharpens the same skills your degree expects you to demonstrate.
Aligned coursework coming soon.
Skills
Skills you'll demonstrate.
Each one shows up on your verified credential.
- Hardware Accelerators
Apply hardware accelerators to solve real industry problems and demonstrate production-level capability.
- Datapath Design
Apply datapath design to solve real industry problems and demonstrate production-level capability.
- Performance Modeling
Apply performance modeling to solve real industry problems and demonstrate production-level capability.
- Memory Subsystems
Apply memory subsystems to solve real industry problems and demonstrate production-level capability.
- Instruction Sets
Apply instruction sets to solve real industry problems and demonstrate production-level capability.
- Stakeholder Communication
Apply stakeholder communication to solve real industry problems and demonstrate production-level capability.
Careers
Career paths this challenge builds toward
Completing this challenge demonstrates skills that transfer directly to these roles:
Hardware Systems Architect
Architects evaluate which functions deserve dedicated silicon and justify the trade-offs. This challenge rehearses exactly that: turning a software hot spot into a hardware datapath proposal and defending its area and power cost against competing blocks.
This challenge sharpens
- hardware-accelerators
- datapath-design
- performance-modeling
Performance / Modeling Engineer
Modeling engineers turn process norms and baselines into defensible estimates that drive design decisions. Here you build the throughput, energy-per-pixel, and area model with sensitivity bounds and tie every figure back to a source.
This challenge sharpens
- performance-modeling
- memory-subsystems
- stakeholder-communication
SoC Design Engineer
System-on-chip engineers size on-chip memory and integrate accelerator blocks under tight area budgets. This challenge exercises line-buffer sizing, datapath layout, and the communication needed to win a silicon slot.
This challenge sharpens
- datapath-design
- memory-subsystems
- hardware-accelerators