Custom Accelerator Sketch for an Image-Processing Pipeline
Overview
What this challenge is about.
Read the current C reference implementation of the 5x5 Gaussian blur (provided). Sketch a parallel datapath that produces 1 output pixel per cycle using a sliding 5x5 window over a line buffer. Specify SRAM line-buffer sizing for 1080p input. Estimate area and dynamic power using published per-mm-squared and per-mW norms for the target 12nm process. Compare to the CPU baseline on throughput, energy per pixel, and area cost. Deliver block diagram (Excalidraw), datapath details, area/power estimates, and a 12-page concept document with a go/no-go recommendation.
The Brief
What you'll do, and what you'll demonstrate.
Sketch a custom 5x5 Gaussian-blur accelerator at the architectural level with area, power, and throughput estimates good enough to win or lose the silicon slot.
Earning criteria — what you'll demonstrate
- Sketch a fixed-function accelerator at the architectural level
- Size SRAM line buffers for streaming image workloads
- Estimate area and power without RTL using published process norms
- Communicate accelerator economics to a chip planning audience
Program Fit
Where this fits in your program.
Sharpens the same skills your degree expects you to demonstrate.
Skills
Skills you'll demonstrate.
Each one shows up on your verified credential.
Careers
Roles this prepares you for.
Real titles. Real skill bridges. Pick the one closest to your trajectory.
Product Manager
PMs on hardware products who understand silicon-area economics make realistic feature trade-offs that survive contact with chip planning.
This challenge sharpens
- stakeholder-communication
- performance-modeling
- hardware-accelerators