Build a UART Receiver and Loopback on FPGA for an Industrial Sensor Hub
Overview
What this challenge is about.
Design a UART receiver in Verilog with 16x oversampling, configurable baud divisor, start-bit detection, 8N1 framing, framing-error flag. Pair with a minimal transmitter for the loopback. Write a testbench that exercises 9600, 115200, and 1 Mbps baud rates with bit-flip injection on the framing tests. Synthesize for Digilent Arty A7 (Xilinx XC7A35T). Validate end-to-end against a USB-to-UART adapter sending random byte streams. Deliver source, testbench, simulation results, the bitstream, a hardware-test report, and a 5-page design document.
The Brief
What you'll do, and what you'll demonstrate.
Design and verify a 16x-oversampled Verilog UART receiver across 3 baud rates and prove it on an Arty A7 against a real USB-to-UART adapter.
Earning criteria — what you'll demonstrate
- Implement a UART receiver with proper oversampling and framing
- Handle metastability on asynchronous inputs with a 2-flip-flop synchronizer
- Verify across multiple baud rates with bit-flip injection
- Validate on hardware against a real external transmitter
Program Fit
Where this fits in your program.
Sharpens the same skills your degree expects you to demonstrate.
Skills
Skills you'll demonstrate.
Each one shows up on your verified credential.
Careers
Roles this prepares you for.
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