Design a 7-Segment Display Controller for a Coffee-Roaster Console
Overview
What this challenge is about.
Design the controller in Verilog: 4-bit BCD (binary-coded decimal) to 7-segment decoder, time-multiplexed digit refresh at 1 kHz per digit, brightness PWM input from MCU, decimal-point control. Write a testbench covering all decode values, refresh timing, and brightness levels. Synthesize for Lattice iCE40 (open-source toolchain), program the dev board, and demonstrate displaying the 4 digits with adjustable brightness. Deliver source, testbench, simulation waveforms, the FPGA bitstream, a short demo video, and a 4-page design document.
The Brief
What you'll do, and what you'll demonstrate.
Design, verify in simulation, and bring up on iCE40 hardware a 4-digit 7-segment display controller with brightness PWM and BCD input.
Earning criteria — what you'll demonstrate
- Implement a small but real Verilog controller end-to-end
- Write a testbench that exercises edge cases, not just happy path
- Synthesize for an open-source FPGA toolchain
- Document a hardware module clearly enough for IP reuse
Program Fit
Where this fits in your program.
Sharpens the same skills your degree expects you to demonstrate.
Skills
Skills you'll demonstrate.
Each one shows up on your verified credential.
Careers
Roles this prepares you for.
Real titles. Real skill bridges. Pick the one closest to your trajectory.
Career mappings coming soon.