Overview
What this challenge is about.
Study the DSL's IR (provided, MLIR-based with linalg-style ops). Choose a tiling strategy (rectangular tiling with cost-modeled tile sizes is the safe baseline; full polyhedral scheduling is the stretch goal). Implement as an MLIR pass that tiles affine loops and updates dependence information. Benchmark 8 representative programs on a workstation-class machine and report cache-miss reductions plus end-to-end speedups. Deliver the pass, benchmark report, and a 10-page design document explaining the tile-size selection heuristic.
The Brief
What you'll do, and what you'll demonstrate.
Design and prototype a polyhedral loop-tiling strategy for a tensor DSL, measured on 8 programs with cache-miss and end-to-end speedup metrics.
Earning criteria — what you'll demonstrate
- Apply polyhedral or affine loop-tiling techniques to a real IR
- Reason about cache locality via measured miss rates, not heuristics alone
- Work inside the MLIR ecosystem on a non-trivial pass
- Design and document a tile-size selection heuristic
Program Fit
Where this fits in your program.
Sharpens the same skills your degree expects you to demonstrate.
Skills
Skills you'll demonstrate.
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Roles this prepares you for.
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