Overview
What this challenge is about.
Fork the project repository and port the synchronous IPC fast path to RISC-V (RV64GC). Preserve the existing fast-path invariants: register-only message passing for messages under 64 bytes, scheduler-coupled direct switch, and capability-based access control. Validate with the existing IPC test suite (must pass 100 percent) and with the project's micro-benchmark harness. Benchmark IPC round-trip latency on a SiFive HiFive board (or QEMU equivalent) against published x86-64 numbers. Deliver the patch series, benchmark results, and a 5-page design document covering register allocation, calling convention, and known limitations.
The Brief
What you'll do, and what you'll demonstrate.
Port a microkernel's synchronous IPC fast path from x86-64 to RISC-V with full test-suite parity and benchmarked latency.
Earning criteria — what you'll demonstrate
- Read and write architecture-specific kernel assembly
- Reason about calling convention and register allocation for IPC
- Validate correctness of a kernel port via property-style tests
- Communicate kernel design decisions to a conservative review audience
Program Fit
Where this fits in your program.
Sharpens the same skills your degree expects you to demonstrate.
Skills
Skills you'll demonstrate.
Each one shows up on your verified credential.
Careers
Roles this prepares you for.
Real titles. Real skill bridges. Pick the one closest to your trajectory.
Career mappings coming soon.