Risc V
If you like applying Risc V, every challenge here gives you a chance to practice it on a real industry brief.
- CodeExpertNew
Port a Microkernel IPC Mechanism to a New Architecture
Fork the project repository and port the synchronous IPC fast path to RISC-V (RV64GC). Preserve the existing fast-path invariants: register-only message passing for messages und…
- Microkernels
- Ipc
- Risc V
Advanced Operating Systems - CodeExpertNew
Implement a Pipelined RISC-V (RV32I) Core for Automotive Telemetry
Implement a classic 5-stage RV32I pipeline in SystemVerilog. Include data-forwarding from EX/MEM and MEM/WB back to EX, a load-use stall, and branch resolution in EX with a 1-cy…
- Systemverilog
- Risc V
- Pipelining
Digital Systems Design
How it works
From brief to credential, in six steps.
Step 01
Browse challenges aligned to your studies.
Step 02
Accept the one that fits your goals.
Step 03
Work through it with AI Copilot guidance.
Step 04
Submit for structured evaluation.
Step 05
Earn a verified credential.
Step 06
Add it to LinkedIn with one click.
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