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Implement a Pipelined RISC-V (RV32I) Core for Automotive Telemetry

FreeVerified credential8 weeksExpert

Overview

What this challenge is about.

Design a pipelined RISC-V core with forwarding and stalls, run compliance tests and benchmarks, and earn a verifiable certificate.

The scenario

The automotive supplier (anonymized; publicly listed, customers across the German OEM ecosystem, ISO 26262 functional-safety processes) wants the core as a starting point for a future ASIL-B (Automotive Safety Integrity Level B) hardened variant.

CredentialBlockchain-anchored
ShareableLinkedIn-ready
LanguageEnglish
PaceSelf-paced

The Brief

What you'll do, and what you'll demonstrate.

Implement a 5-stage pipelined RV32I core in SystemVerilog with hazard handling, pass the RISC-V compliance tests, and benchmark CPI on telemetry workloads.

Earning criteria — what you'll demonstrate

  • Implement a classic 5-stage pipeline with data forwarding and stall logic
  • Resolve branches in the right stage and quantify the penalty
  • Pass the official RISC-V compliance suite
  • Measure and reason about CPI on real workloads

Program Fit

Where this fits in your program.

Sharpens the same skills your degree expects you to demonstrate.

Digital Systems Design

Bachelor · Embedded And Iot

Strong alignment

This challenge maps to Digital Systems Design at the Bachelor level. It sharpens the same practical skills your coursework expects — but in a real industry context with actual constraints and deliverables.

One more thing

You can put a credential on your CV by Friday.