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Implement a Pipelined RISC-V (RV32I) Core for Automotive Telemetry

FreeVerified credential8 weeksExpert

Overview

What this challenge is about.

Implement a Pipelined RISC-V (RV32I) Core for Automotive Telemetry. Expert-level challenge in code. Writing production code that solves real engineering prob...

CredentialBlockchain-anchored
ShareableLinkedIn-ready
LanguageEnglish
PaceSelf-paced

The Brief

What you'll do, and what you'll demonstrate.

Implement a 5-stage pipelined RV32I core in SystemVerilog with hazard handling, pass the RISC-V compliance tests, and benchmark CPI on telemetry workloads.

This is not a coding exercise. It is the work a software engineer does between a Jira ticket and a merged PR. That distinction matters to every hiring manager who has seen candidates solve LeetCode problems and none who have shipped production code under real constraints.

When you finish, you will have something most graduates do not: a real-world deliverable, verified by Ewance, that you can show to a hiring manager and say "I did this. Here is the proof."

Earning criteria — what you'll demonstrate

  • Implement a classic 5-stage pipeline with data forwarding and stall logic
  • Resolve branches in the right stage and quantify the penalty
  • Pass the official RISC-V compliance suite
  • Measure and reason about CPI on real workloads

Program Fit

Where this fits in your program.

Sharpens the same skills your degree expects you to demonstrate.

Digital Systems Design

Bachelor · Embedded And Iot

Strong alignment

This challenge maps to Digital Systems Design at the Bachelor level. It sharpens the same practical skills your coursework expects — but in a real industry context with actual constraints and deliverables.

One more thing

You can put a credential on your CV by Friday.