Implement a Pipelined RISC-V (RV32I) Core for Automotive Telemetry
Overview
What this challenge is about.
Implement a classic 5-stage RV32I pipeline in SystemVerilog. Include data-forwarding from EX/MEM and MEM/WB back to EX, a load-use stall, and branch resolution in EX with a 1-cycle penalty. Hook up a simple instruction-memory and data-memory model. Run the official RISC-V compliance test suite (riscv-tests) in simulation. Measure CPI (cycles per instruction) on a small set of provided telemetry-style benchmarks (FIR filter, CRC32, sliding-window average). Deliver source, simulation results, compliance-test pass logs, performance benchmark report, and an 8-page architecture document.
The Brief
What you'll do, and what you'll demonstrate.
Implement a 5-stage pipelined RV32I core in SystemVerilog with hazard handling, pass the RISC-V compliance tests, and benchmark CPI on telemetry workloads.
Earning criteria — what you'll demonstrate
- Implement a classic 5-stage pipeline with data forwarding and stall logic
- Resolve branches in the right stage and quantify the penalty
- Pass the official RISC-V compliance suite
- Measure and reason about CPI on real workloads
Program Fit
Where this fits in your program.
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Skills
Skills you'll demonstrate.
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Roles this prepares you for.
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