Systemverilog
If you like applying Systemverilog, every challenge here gives you a chance to practice it on a real industry brief.
- CodeExpertNew
Implement a Pipelined RISC-V (RV32I) Core for Automotive Telemetry
Implement a classic 5-stage RV32I pipeline in SystemVerilog. Include data-forwarding from EX/MEM and MEM/WB back to EX, a load-use stall, and branch resolution in EX with a 1-cy…
- Systemverilog
- Risc V
- Pipelining
Digital Systems Design - CodeAdvancedNew
FPGA-Based Convolution Accelerator for an Embedded Vision Camera
Design the accelerator as an AXI-Stream block: input video stream, line-buffer-based 3x3 windowing, fixed-point multiply-accumulate tree, output stream. Parameterize for arbitra…
- Systemverilog
- Fpga
- Axi Stream
Digital Systems Design
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