FPGA-Based Convolution Accelerator for an Embedded Vision Camera
Overview
What this challenge is about.
Design the accelerator as an AXI-Stream block: input video stream, line-buffer-based 3x3 windowing, fixed-point multiply-accumulate tree, output stream. Parameterize for arbitrary 3x3 kernel coefficients. Write a Python reference model and a SystemVerilog testbench that cross-checks the hardware output against the reference on 4 test frames. Synthesize for Zynq UltraScale+ ZCU102. Measure LUT (lookup table) and DSP (digital signal processing) block utilization, plus achieved fps. Deliver source, the reference model, testbench, synthesis report, on-hardware throughput measurement, and a 10-page design document.
The Brief
What you'll do, and what you'll demonstrate.
Build a 3x3 convolution AXI-Stream accelerator in SystemVerilog that runs 60 fps on 1920x1080 grayscale on Zynq UltraScale+ within budget.
Earning criteria — what you'll demonstrate
- Design a dataflow accelerator using AXI-Stream interfaces
- Implement line-buffer-based windowing for streaming image processing
- Cross-check hardware output against a software reference model
- Reason about LUT/DSP budgets and throughput trade-offs
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Where this fits in your program.
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Skills
Skills you'll demonstrate.
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