Verilog
If you like applying Verilog, every challenge here gives you a chance to practice it on a real industry brief.
- CodeIntermediateNew
Build a 5-Stage Pipelined RISC-V Core in Verilog
Implement the 5-stage pipeline with: hazard detection unit, forwarding paths (EX/MEM to EX, MEM/WB to EX), pipeline stalls for load-use hazards, and a simple static branch-not-t…
- Pipelining
- Hazard Detection
- Verilog
Computer Architecture - DesignBeginnerNew
Design a Verified UART Receiver and Loopback for an FPGA Sensor Hub
Propose and deliver a UART receiver for Helax's sensor hub that meets the functional requirements in the requirements brief (the 'uart-requirements-brief' material): 16-times ov…
- Verilog
- Uart
- Fpga
Open coursework - CodeFoundationalNew
Design and Verify a 7-Segment Roaster-Console Display Controller
Working only from the materials provided, build and verify the controller. Implement the controller per the signal definitions in the microcontroller interface specification (ic…
- Verilog
- Fpga
- Digital Logic
Open coursework
How it works
From brief to credential, in six steps.
Step 01
Browse challenges aligned to your studies.
Step 02
Accept the one that fits your goals.
Step 03
Work through it with AI Copilot guidance.
Step 04
Submit for structured evaluation.
Step 05
Earn a verified credential.
Step 06
Add it to LinkedIn with one click.
Industry teams behind a decade of practitioner briefs
Hiring from this pool?
Sponsor a challenge and meet candidates through actual work.
Industry teams can shape briefs around the skills they hire for, then evaluate students on rubric-scored deliverables — not resumes.